The VHDL codes generated for the various signal processing steps were downloaded into a Cyclone FPGA chip around which the ultrasonic ranger had been built.
![nco dsp builder nco dsp builder](https://s3.manualzz.com/store/data/025966353_1-466d6bd8e3c246831ff57015793d9d7d-360x466.png)
The percentage phase error for the range 0.6m to 6m is about 0.2. The pulse frequency of the numerically controlled oscillator (NCO) is extremely accurate, enabling fine tuning of the SDFT and RPLL also improves the lock time for the 50Hz input signal to 0.04s. Further, the quadrature signal is reinforced by another cosine signal derived from a lookup table (LUT). A new RPLL is described in which the phase error is driven to zero using the quadrature signal derived from the SDFT. Numerically controlled oscillator (NCO) is commonly used in a FPGA module, in the Digital Signal Processing.
#Nco dsp builder series
The extracted envelopes are filtered by SDFT without introducing any additional phase shift. This article is the first in the series 15.
![nco dsp builder nco dsp builder](https://d3i71xaburhd42.cloudfront.net/0e8339c7013768000a93b65896afa05320a00f15/1-Figure2-1.png)
The phase shift between the envelope of the reference IR pilot signal and that of the received ultrasonic signal is proportional to the range. f For information about interoperability with the DSP Builder standard blockset, refer to the DSP Design Flow User Guide. This range finder principally utilizes amplitude-modulated ultrasonic waves assisted by an infrared (IR) pilot signal. The advanced blockset can be used enti rely independently of the DSP Builder standard blockset, or can be embedded within top-level DSP Builder designs. An accurate ultrasonic range finder employing Sliding Discrete Fourier Transform (SDFT) based restructured phase-locked loop (RPLL), which is an improved version of the recently proposed integrated phase-locking scheme (IPLL), has been expounded.